Let the input signal swings form +10 V to -10 V. During first negative half cycle as Vi rises from 0 to -10 V, the diode conducts. Assuming an ideal diode, its voltage, which is also the output must be zero during the time from 0 to t1. The capacitor charges during this period to 10 V, with the polarity shown.
After that V
i starts to drop which means the anode of D is negative relative to cathode, (V
D= v
i - v
C) thus reverse biasing the diode and preventing the capacitor from discharging.
Fig. 2. Since the capacitor is holding its charge it behaves as a DC voltage source while the diode appears as an open circuit, therefore the equivalent circuit becomes an input supply in series with +10 V dc voltage and the resultant output voltage is the sum of instantaneous input voltage and dc voltage (+10 V).
To clamp the input signal by a voltage other than peak value, a dc source is required. As shown in
fig. 3, the dc source is reverse biasing the diode.
The input voltage swings from +10 V to -10 V. In the negative half cycle when the voltage exceed 5V then D conduct. During input voltage variation from –5 V to -10 V, the capacitor charges to 5 V with the polarity shown in
fig. 3. After that D becomes reverse biased and open circuited. Then complete ac signal is shifted upward by 5 V. The output waveform is shown in
fig. 4.
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