The biasing circuit based on single power supply is shown in fig. 1. This is similar to the voltage divider bias used with a bipolar transistor.
Fig. 1
The Thevenin voltage VTH applied to the gate is
The Thevenin resistance is given as
The gate current is assumed to be negligible. VTH is the dc voltage from gate to ground.
The drain current ID is given by
and the dc voltage from the drain to ground is VD = VDD – ID RD.
If VTH is large enough to swamp out VGS the drain current is approximately constant for any JFET as shown in fig. 2.
Fig. 2
There is a problem in JFET. In a BJT, VBE is approximately 0.7V, with only minor variations from one transistor to other. In a FET, VGS can vary several volts from one JFET to another. It is therefore, difficult to make VTH large enough to swamp out VGS. For this reason, voltage divider bias is less effective with, FET than BJT. Therefore, VGS is not negligible. The current increases slightly from Q2 to Q1. However, voltage divider bias maintains ID nearly constant.
Consider a voltage divider bias circuit shown in fig. 3.
Difference in ID (min) and ID (max) is less
VD (max) = 30 – 2.13 * 4.7 = 20 V
VD (min) = 30 – 2.67 * 4.7 = 17.5 V
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