Transductance Curves:
The transductance curve of a JFET is a graph of output current (ID) vs input voltage (VGS) as shown in fig. 1.
Fig. 1
By reading the value of ID and VGS for a particular value of VDS, the transductance curve can be plotted. The transductance curve is a part of parabola. It has an equation of
Data sheet provides only IDSS and VGS(off) value. Using these values the transductance curve can be plotted.
Biasing the FET:
The FET can be biased as an amplifier. Consider the common source drain characteristic of a JFET. For linear amplification, Q point must be selected somewhere in the saturation region. Q point is selected on the basis of ac performance i.e. gain, frequency response, noise, power, current and voltage ratings.
Gate Bias:
Fig. 2, shows a simple gate bias circuit.
Fig. 2
Separate VGS supply is used to set up Q point. This is the worst way to select Q point. The reason is that there is considerable variation between the maximum and minimum values of FET parameters e.g.
| |
IDSS
|
VGS(off)
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| Minimum |
4mA
|
-2V
|
| Maximum |
13mA
|
-8V
|
This implies that the minimum and maximum transductance curves are displaced as shown in fig. 3.
Gate bias applies a fixed voltage to the gate. This fixed voltage results in a Q point that is highly sensitive to the particular JFET used. For instance, if VGS= -1V the Q point may very from Q1 to Q2depending upon the JFET parameter is use.
At Q1, ID= 0.016 (1 - (1/8))2 = 12.3 mA
At Q2, ID= 0.004 (1-(1/2))2 = 1 mA.
The variation in drain current is very large.
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Fig. 3
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